1. Field of the Invention
The present invention relates to a solid-state imaging device, a driving control method, and an imaging apparatus.
2. Description of Related Art
As a solid-state imaging device, a complementary metal-oxide semiconductor (CMOS) image sensor of a column parallel analog-digital (AD) conversion scheme (hereinafter called a column AD conversion scheme) has been proposed in which pixels are disposed two-dimensionally in a matrix shape and an analog-digital converter (ADC) is disposed for each column.
In recent years, a column AD conversion scheme CMOS image sensor improved to be suitable for high speed image capturing has been proposed. For example, Japanese Unexamined Patent Application Publication No. 2005-278135 discloses a column AD conversion scheme CMOS image sensor which achieves, by using up-down counters, a high frame rate and a high resolution without increasing a circuit scale.
FIG. 1 shows a configuration example of an ADC 1 of a column AD conversion scheme CMOS image sensor.
The ADC 1 includes as many column AD circuits 11 as the number of columns of pixels two-dimensionally disposed in a matrix shape, and pixel signals outputted from the respective pixels in the same column are subjected to an AD conversion in a time division manner at a corresponding column AD circuit 11.
In the column AD circuit 11, a reference signal from a digital-analog converter (DAC, not shown) is inputted via a capacitance element 12 to a comparator 14, and a pixel signal outputted from each pixel is inputted via a capacitance element 13 to the comparator 14. A reference signal supplied from DAC is a signal of a so-called ramp waveform which changes its level (voltage) in a slope shape with a lapse of time. The capacitance elements 12 and 13 remove DC components of the reference and pixel signals so that only AC components of the reference and pixel signals can be compared at the comparator 14.
The comparator 14 outputs a difference signal obtained through a comparison between the pixel signal and the reference signal to an up/down counter 15. When the reference signal is larger than the pixel signal, a difference signal at a high level is supplied to the up/down counter 15, whereas when the reference signal is smaller than the pixel signal, a difference signal at a low level is supplied to the up/down counter 15.
The up/down counter (U/D CNT) 15 down-counts in a pre-charge phase (P-phase) ADC enable period only while a difference signal at a high level is supplied, and up-counts in a data phase (D-phase) ADC enable period only while a difference signal at a high level is supplied. The P-phase ADC enable period is a period while reset components ΔV are measured which are pixel variation components, and the D-phase ADC enable period is a period while (signal components Vsig+reset components ΔV) are measured. By combining a count in the P-phase ADC enable period and a count in the D-phase ADC enable period, only the signal components Vsig which are (signal components Vsig+reset components ΔV)−(reset components ΔV) can be obtained to implement a CDS processing.
In the column AD conversion scheme CMOS image sensor having the ADC constructed as above, when it is necessary to perform pixel addition, the pixel addition processing is performed at a processing block after the up/down counter 15. Accordingly, a driving method for the ADC 1 is not different between performing pixel addition and not performing pixel addition, and a power consumption of the ADC 1 is the same for both performing pixel addition and not performing pixel addition.
In another method for pixel addition, a common floating diffusion (FD) portion is used for adjacent pixels in a vertical direction (column direction) in a pixel array having pixels two-dimensionally disposed in a matrix shape, to thereby perform pixel addition of the adjacent pixels in the vertical direction.
FIG. 2 shows a configuration example of a pixel array in which pixel addition of adjacent pixels in the vertical direction is performed by using a common FD portion of the adjacent pixels in the vertical direction.
Of pixels 21A and 21B adjacent in the vertical direction shown in FIG. 2, the pixel 21A includes a photodiode 31A and a transfer transistor 32A for transferring charges to an FD portion, and the pixel 21B includes a photodiode 31B and a transfer transistor 32B for transferring charges to the FD portion. A selection transistor 34 and an amplifier transistor 35 are provided in common for the pixels 21A and 21B.
In this case, by turning on the transfer transistors 32A and 32B at the same time, charges accumulated in the photodiode 31A and charges accumulated in the photodiode 31B are added together in a portion indicated by a broken line in FIG. 2. The added pixel signal is supplied to a comparator 14 because the drain of the amplifier transistor 35 is connected to a constant current source 36 and to a capacitance element 13 of a column AD circuit 11. Accordingly, pixel addition is performed for adjacent pixels in the vertical direction.